Part 1 | 12 Easy Verilog/SV Projects | The Silicon Sandbox скачать в хорошем качестве

Part 1 | 12 Easy Verilog/SV Projects | The Silicon Sandbox

𝐏𝐚𝐫𝐭 𝟏 (𝐄𝐚𝐬𝐲 𝐋𝐞𝐯𝐞𝐥 𝐏𝐫𝐨𝐣𝐞𝐜𝐭𝐬) 🔥 𝐌𝐚𝐬𝐭𝐞𝐫 𝐑𝐓𝐋 𝐃𝐞𝐬𝐢𝐠𝐧 (𝐏𝐚𝐫𝐭 𝟏/𝟑): 𝟏𝟐 𝐄𝐚𝐬𝐲 𝐕𝐞𝐫𝐢𝐥𝐨𝐠/𝐒𝐲𝐬𝐭𝐞𝐦𝐕𝐞𝐫𝐢𝐥𝐨𝐠 𝐏𝐫𝐨𝐣𝐞𝐜𝐭𝐬 𝐭𝐨 𝐁𝐮𝐢𝐥𝐝 𝐘𝐨𝐮𝐫 𝐅𝐨𝐮𝐧𝐝𝐚𝐭𝐢𝐨𝐧! Starting your VLSI journey? These beginner-friendly RTL projects help you master digital logic, FSMs, and basic communication protocols. 📚 𝐄𝐚𝐬𝐲 𝐋𝐞𝐯𝐞𝐥 𝐏𝐫𝐨𝐣𝐞𝐜𝐭𝐬 𝟏. 𝐅𝐒𝐌 𝐃𝐞𝐬𝐢𝐠𝐧 (𝐕𝐞𝐧𝐝𝐢𝐧𝐠 𝐌𝐚𝐜𝐡𝐢𝐧𝐞, 𝐒𝐞𝐪𝐮𝐞𝐧𝐜𝐞 𝐃𝐞𝐭𝐞𝐜𝐭𝐨𝐫, 𝐞𝐭𝐜.) – Implements sequential behavior using defined states and transitions. 𝟐. 𝟏×𝟑 𝐑𝐨𝐮𝐭𝐞𝐫 – Routes incoming data to one of three output ports based on control logic. 𝟑. 𝐀𝐋𝐔 (𝐀𝐫𝐢𝐭𝐡𝐦𝐞𝐭𝐢𝐜 𝐋𝐨𝐠𝐢𝐜 𝐔𝐧𝐢𝐭) – Performs ADD, SUB, AND, OR, XOR, shifts, and comparisons. 𝟒. 𝐓𝐫𝐚𝐟𝐟𝐢𝐜 𝐋𝐢𝐠𝐡𝐭 𝐂𝐨𝐧𝐭𝐫𝐨𝐥𝐥𝐞𝐫 – Controls a 4-way junction using timed state transitions. 𝟓. 𝐔𝐀𝐑𝐓 𝐈𝐦𝐩𝐥𝐞𝐦𝐞𝐧𝐭𝐚𝐭𝐢𝐨𝐧 – Designs serial TX/RX with baud generator and framing. 𝟔. 𝐒𝐏𝐈 𝐌𝐚𝐬𝐭𝐞𝐫/𝐒𝐥𝐚𝐯𝐞 – Implements CPOL/CPHA modes with full-duplex communication. 𝟕. 𝐏𝐖𝐌 𝐆𝐞𝐧𝐞𝐫𝐚𝐭𝐨𝐫 – Produces PWM signals with adjustable duty cycle and frequency. 𝟖. 𝟕-𝐒𝐞𝐠𝐦𝐞𝐧𝐭 𝐃𝐢𝐬𝐩𝐥𝐚𝐲 𝐂𝐨𝐧𝐭𝐫𝐨𝐥𝐥𝐞𝐫 – Converts BCD to 7-segment outputs with multiplexing. 𝟗. 𝐁𝐚𝐬𝐢𝐜 𝟒-𝐛𝐢𝐭 𝐀𝐫𝐢𝐭𝐡𝐦𝐞𝐭𝐢𝐜 𝐔𝐧𝐢𝐭 – Performs 4-bit addition, subtraction, multiplication, and division. 𝟏𝟎. 𝐒𝐏𝐈 𝐏𝐫𝐨𝐭𝐨𝐜𝐨𝐥 (𝐁𝐞𝐠𝐢𝐧𝐧𝐞𝐫) – Implements basic synchronous SPI communication. 𝟏𝟏. 𝐔𝐀𝐑𝐓 (𝐁𝐞𝐠𝐢𝐧𝐧𝐞𝐫 𝐕𝐚𝐫𝐢𝐚𝐧𝐭) – Simple serial communication controller. 𝟏𝟐. 𝐒𝐢𝐦𝐩𝐥𝐞 𝐈𝐦𝐚𝐠𝐞 𝐅𝐢𝐥𝐭𝐞𝐫𝐬 – Implements median filter and edge-detection logic. 🔜 𝐏𝐚𝐫𝐭 𝟐 (𝐌𝐞𝐝𝐢𝐮𝐦-𝐋𝐞𝐯𝐞𝐥 𝐏𝐫𝐨𝐣𝐞𝐜𝐭𝐬) 𝐜𝐨𝐦𝐢𝐧𝐠 s𝐨𝐨𝐧! #VLSI #RTLDesign #Verilog #SystemVerilog #Semiconductors #TheSiliconSandbox