Accelerating Designs for SoC FPGA Using Simplified High-Level Synthesis Flows - Manuel Saldana скачать в хорошем качестве

Accelerating Designs for SoC FPGA Using Simplified High-Level Synthesis Flows - Manuel Saldana

Accelerating Designs for SoC FPGA Using Simplified High-Level Synthesis Flows - Manuel Saldana, Microchip Modern FPGA devices include tightly coupled CPUs into their reconfigurable fabric providing more architectural options to developers when implementing and optimizing designs for power, area and performance. Designing for these types of devices requires mixing software and hardware components and compilation flows, which can be a complex process. Having the right tools and examples can enhance the development experience and simplify the architectural exploration process. This talk will present an end-to-end example of an interactive, real-time, H264-encoded video streaming application over the network that can be controlled via a web browser. The emphasis of the presentation will be on how video processing functions can be easily added to the video processing pipeline in the FPGA fabric using C++ and how they can interact with RISC-V CPUs. Different aspects of the design will be covered, such as software-hardware partitioning, automatic C++ driver API generation, automatic integration of the accelerator modules, DMA burst transfers and testing and verification mechanisms for individual processing functions. We will discuss performance comparisons between video processing in the FPGA compared to the RISC-V cores using the frames-per- second and CPU utilization. The design uses a common control-plane-data-plane design pattern that could be used as a starting point for other streaming applications as well.