[UR] Computer Architecture Sessional-II Prep Guide, Spring 2026 FAST NUCES LHR скачать в хорошем качестве

[UR] Computer Architecture Sessional-II Prep Guide, Spring 2026 FAST NUCES LHR

Everything FAST-NUCES LHR Related I've Put Out: https://docs.google.com/document/d/1e... Timestamps: 0:00 - Start 0:09 - Single v. Multi-Cycle Architecture 3:20 - Pipelining 4:24 - Pipeline Hardware Behavior Details 10:52 - Control Path Propagation in Pipelining 14:34 - Pipeline Hazards 14:42 - Structural Hazards 16:00 - Data Hazards (EM Hazard) 16:41 - Forwarding in EX Data Hazards 17:30 - Data Hazards (MEM Hazard) 18:45 - Stall Cycles (NOPs and Re-fetching) 22:03 - Forwarding Hardware 25:22 - Hazard Detection Hardware 27:02 - Control (Branch) Hazards 27:34 - Delayed Branch 28:35 - Static Branch Prediction 31:50 - Implications of Branch Resolution at EX v. at ID 33:33 - Dynamic Branch Prediction (Branch History Tables) 33:41 - 1-Bit Branch Predictor 37:31 - 2-Bit Branch Predictor 38:26 - Performance Comparison Example 40:39 - (m,n) Correlating Predictor 43:20 - Problem Examples 46:10 - Branch Target Buffer (BTB) 48:11 - Exceptions (SCAUSE, SEPC, IVT) 49:32 - Hardware View 50:49 - Precise Exceptions 51:20 - Instruction Level Parallelism and Out of Order Completion 52:39 - Data Hazards in OoOC 55:07 - Latency and Initiation Interval 57:24 - Imprecise Exceptions due to OoOC 58:34 - Memory Ambiguity Problem 59:27 - Name Dependencies 1:01:19 - Scheduling 1:02:12 - Static ('Compiler') Scheduling 1:02:35 - Reordering Instructions 1:05:00 - Loop Unrolling 1:06:18 - Loop Unrolling + Reordering + Renaming 1:07:40 - Dynamic ('Hardware') Scheduling 1:08:09 - Reorder Buffer (ROB) 1:11:00 - Single v. Wide-Issue Processors 1:11:41 - VLIW (Very Long Instruction Word) Architecture 1:13:14 - Superscalar Architecture 1:13:35 - MicroOps in CISC 1:14:32 - End