Zdenek Prikryl, Codasip - RISC-V as an Enabler of Heterogeneous Compute скачать в хорошем качестве

Zdenek Prikryl, Codasip - RISC-V as an Enabler of Heterogeneous Compute

Zdenek Prikryl, CTO, Codasip – RISC-V as an enabler of heterogeneous compute Abstract The semiconductor industry has benefited from shrinking process nodes to improve performance while reducing cost and power for many years. But this no longer holds. We can’t rely on smaller silicon geometries to achieve computational improvements. Instead, we are in a world where performance, power, and cost benefits must come from the architecture and from custom compute. With many possible specialized processor architectures, processor design automation is essential to ensure that design cycles are short and cost-effective. In this demo, we will go through some examples that show how RISC-V designs are customized for computational workloads in different domains using a single, unified toolchain for processor design automation.