Using Formal to Vaccinate RISC-V Designs Against Catastrophic Bugs - Dr. Ashish Darbari, AXIOMISE скачать в хорошем качестве

Using Formal to Vaccinate RISC-V Designs Against Catastrophic Bugs - Dr. Ashish Darbari, AXIOMISE

Using Formal to Vaccinate RISC-V Designs Against Catastrophic Bugs - Dr. Ashish Darbari, AXIOMISE Bug escapes in silicon lead to catastrophic failures – well-known being the Intel FDIV bug, Ariane 5 explosion, and several ongoing security vulnerabilities affecting almost all the computing devices. Formal verification provides exhaustive proofs of bug absence, as well as efficient bug-hunting. The use of formal methods in chip designs prevents bugs to creep in ensuring the chips remain clean, not exhibiting any symptoms of bugs – almost the same way as humans react when they are vaccinated against life-threatening bugs. So, is "formal verification" the vaccine that chip design needs to keep itself safe from bugs? Dr. Darbari believes it is. In this talk, he presents a methodology and an APP that can be used to find bugs both in designs-under-development and in pre-verified processors. The methodology shown is able to prove the bug absence using any formal verification tool.