Mastering Xilinx DSP IP cores on Zynq 7000: FIR, CIC, DDS, FFT скачать в хорошем качестве

Mastering Xilinx DSP IP cores on Zynq 7000: FIR, CIC, DDS, FFT

This hands-on course covers four essential Xilinx DSP IP cores: FIR Compiler, CIC Compiler, DDS Compiler, and Fast Fourier Transform (FFT). You’ll learn how to configure and simulate each core using Vivado 2024.2, create Verilog testbenches, and analyze the outputs using Python. You'll also learn how to integrate these cores into FPGA designs and write standalone C applications to interface with the IP cores on development boards based on the Zynq-7000 SoC, such as the Arty Z7-20. Additionally, the course teaches you how to automate your development workflow using TCL scripts in Vivado and Vitis, and how to debug hardware designs with System ILA. To obtain course please follow the Udemy link: https://www.udemy.com/course/xlnx-dsp... Or you can get the course directly from me: https://www.fpga-radar.com/xlnx-dsp-ip 0:00 - Introduction 1:55 - Requirements and Workflow Automation 10:10 - Vivado simulation: FIR compiler v7.2 31:56 - Vivado simulation: CIC compiler v4.0 41:59 - Vivado simulation: DDS compiler v6.0 50:59 - Vivado simulation: Fast Fourier Transform v9.1 59:01 - Zynq 7000 SoC: C application to interface with FIR compiler IP cores 1:09:23 - Zynq 7000 SoC: C application to interface with CIC compiler IP cores 1:14:46 - Zynq 7000 SoC: C application to interface with DDS compiler IP cores 1:18:00 - Zynq 7000 SoC: C application to interface with Fast Fourier Transform IP core