How to do a Timing Simulation using Modelsim and Xilinx ISE скачать в хорошем качестве

How to do a Timing Simulation using Modelsim and Xilinx ISE

Learn how to use Modelsim to run a timing simulation for a VHDL design. Using Modelsim PE Student Edition 10.3c, and Xilinx ISE 14.7. the .do file is below Change directory to where the timing files are kept I always create a timing folder in the project directory After running the "Generate post place and route simulation model", move the _timesim.vhd and _timesim.sdf files stored in /netgen/par into the /timing folder cd {C:\Users\Alexander\Dropbox\Class\EL5493 - VHDL\leftrotate32\timing} Create work library vlib work Ensure xilinx libraries are mapped correctly Your xilinx install may be different, so double check this line vmap simprim {C:\Xilinx\14.7\ISE_DS\ISE\vhdl\mti_pe\10.3c
t64\simprim} Compile the file vcom leftRotate32_timesim.vhd Start the simulation and provide the timing information sdftyp uses "typical" delays can also use sdfmax (max delays) or sdfmin (min delays) vsim -sdftyp leftRotate32_timesim.sdf work.leftRotate32 Open waveform window view wave change radix to hex radix hex Add signals to waveform window add wave A B O Force Output A force a 16#915F 0 ns, 16#BE41 100 ns, 16#6355 200 ns, 16#10A9 300 ns Force Output B force b 16#4619 0 ns, 16#B251 100 ns, 16#A501 200 ns, 16#CE91 300 ns run 400 ns