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S7-E4 - Graphene webinar series - Part 4 - Graphenea Process Flow for Versatile Device Architectures ΡΠΊΠ°Ρ‡Π°Ρ‚ΡŒ Π² Ρ…ΠΎΡ€ΠΎΡˆΠ΅ΠΌ качСствС

S7-E4 - Graphene webinar series - Part 4 - Graphenea Process Flow for Versatile Device Architectures 11 months ago

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S7-E4 - Graphene webinar series - Part 4 - Graphenea Process Flow for Versatile Device Architectures
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S7-E4 - Graphene webinar series - Part 4 - Graphenea Process Flow for Versatile Device Architectures

Graphene has come a long way since its discovery roughly 20 years ago. Due to its monoatomic thickness, high carrier mobility and optical absorption, graphene sparked a lot of interest, and a myriad of different device architectures and use cases have been studied in the last decade. Lately, the efforts have been devoted towards the mass production of graphene devices, where significant advancements have been made. The Graphenea MPW targets cutting-edge device architectures for novel applications with graphene. The first part of the talk delivered by dr. Elias Torres (Graphenea) will be a general and brief overview of graphene and the current state of the art in terms of graphene/2D device processing. Some applications/use cases that these devices would be helpful for will be outlined and commented. The second part of the talk by dr. Juan Manuel GΓ³mez PΓ©rez (Graphenea) will take a deeper look at the specifications of MPW #6 with Graphenea Semiconductor. The basic process flow 2.5 (PF2.5) will be introduced and described, as well as design rules constraints to create the best geometry for your application/use case, and the different device architectures one can build from the basic PF2.5 will be discussed as well; due to the high versatility of the PF2.5, only a few device architectures/geometries will be considered, although they will be very relevant for the use cases introduced.

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