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📽️ Ultra Ethernet & UALink: Powering Scalable, Low-Latency AI Networking for Next-Gen Compute The explosive growth of large-scale AI models and multi-node training clusters is straining conventional network interconnects. This session introduces two breakthrough technologies Ultra Ethernet and UALink, that redefine how next-generation AI systems communicate. Ultra Ethernet, driven by leaders such as Intel, AMD, Meta, and Cisco, extends standard Ethernet with AI-centric capabilities including RDMA, advanced congestion control, and packet-spraying. These enhancements cut latency, lower CPU overhead, and enable efficient load balancing across massive data centers. UALink takes a complementary approach with a switched-fabric architecture designed specifically for accelerator-to-accelerator communication. Its direct load/store operations and atomic transaction support deliver ultra-low latency and optimal bandwidth utilization critical for tightly coupled AI accelerator clusters and deterministic scale-up performance. This talk offers a clear technical comparison of the two solutions: Ultra Ethernet excels at broad, heterogeneous scale-out deployments, while UALink drives scale-up, high-density AI systems. Built on open standards, both allow smooth, incremental integration. Real-world deployment examples will highlight how adopting Ultra Ethernet and UALink can boost training throughput, cut infrastructure costs, and enhance accuracy in AI and HPC workloads—preparing infrastructure for the next wave of compute-intensive applications. ------------------------------------------------------------------------------------------------------------------------ 🗣️ Rajesh Arsid / rajesh-arsid-064b4221 Rajesh Arsid is a highly accomplished Principal Engineer in ASIC Physical Design, with extensive experience in the semiconductor industry and a strong track record of delivering complex, high-performance integrated circuit solutions. At Synopsys Inc., he plays a key role in the development of cutting-edge PCIe subsystem architectures, contributing to multiple generations of PCIe and CXL designs that power advanced computing and AI applications. His work has supported major global technology leaders in achieving critical product milestones. Rajesh's technical strengths encompass the entire ASIC physical design flow, from floor planning and clock tree synthesis to power grid architecture, signal integrity, and final tape-out. He brings deep expertise in multi-voltage and low-power design strategies across advanced FinFET and legacy technology nodes. His collaborative leadership style and global team coordination capabilities have enabled the successful execution of complex SoC programs under tight schedules. Throughout his career, Rajesh has contributed to the development of a diverse range of technologies, including 1.6T Ethernet controller, Mult-Core Processor, Storage controllers, GNSS receivers, (RAID)-on-chip storage and fiber-to-the-home SoCs. His ability to drive innovation, optimize design flow methodologies, and resolve critical challenges has earned him numerous accolades for execution excellence, innovation, and customer success. Rajesh holds a Master of Science in Electronics and Communication from Napier Edinburgh University in the United Kingdom and a Bachelor of Engineering from Bangalore University in India. He is also a certified IC Layout Design Engineer through Cadence Design Systems. His commitment to continuous learning, process improvement, and technical mentorship has made him a valuable contributor to the semiconductor design community. ------------------------------------------------------------------------------------------------------------------------ 🍿#DataPopkorn https://www.DataPopkorn.com / datapopkorn Questions? / mikeybronowski #DataCommunity #SQLFamily #mvpbuzz #itpro ------------------------------------------------------------------------------------------------------------------------ 🎵Music by Breakz Studios from Pixabay https://pixabay.com/users/breakzstudi... https://pixabay.com/music/