Wouldn’t it be Convenient? Bart Brosens, Application Engineer, Sigasi скачать в хорошем качестве

Wouldn’t it be Convenient? Bart Brosens, Application Engineer, Sigasi

Have you ever worked with VHDL, Verilog, SystemVerilog or mixed language code? How much time did you lose chasing a trivial syntax issue that resulted in a compilation error? How much time have you lost with missing parentheses in a preprocessor macro? How much time did you spend on a wrong transition in a state machine? How much... In this presentation we’ll show you how you can avoid typical HDL frustrations. We'll show how to be more efficient when reading and writing HDL code, for both RTL and verification. The solution is to use a smart editor which analyzes your code while you type and gives you immediate feedback on your code. This way you can avoid all of the issues above and your code is ready for simulation much faster. You’ll have better focus and the quality of your work will be much higher.