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Welcome to our 10th lecture where we will be having the Question and Answer session of "Good Coding Practices and Design Recommendations for FPGAs 1/3: Reset Usages in FPGAs" 🤓 We will be discussing Asynchronous/Synchronous/No Reset Usages and pros/cons of each case. For your information, I am an FPGA engineer with 15 years of experience, and here is my LinkedIn profile / koray-karakurt You may subscribe and join our YouTube channel in order to support and encourage us 😊 Thanks in advance 🙏 Our Curriculum (6 weeks, 12 lectures) is as follows: WEEK 01 Course-01 (29-SEP-24, at 10 A.M. GMT+2) 8 Major Steps of FPGA Design and Verification https://youtube.com/live/j1uc9wGHP1s Course-02 (29-SEP-24, at 01 P.M. GMT+2) Q&A https://youtube.com/live/77AiCSjF1W0 WEEK 02 Course-03 (02-OCT-24, at 08 P.M. GMT+2) VHDL versus Verilog versus SystemVerilog https://youtube.com/live/kBtmiuDApQQ Course-04 (06-OCT-24, at 10 A.M. GMT+2) Q&A https://youtube.com/live/fWZainGbmSk WEEK 03 Course-05 (09-OCT-24, at 08 P.M. GMT+2) Linting Rules for FPGA Design and Verification https://youtube.com/live/LxKOkrByU9Q Course-06 (09-OCT-24, at 10 P.M. GMT+2) Q&A https://youtube.com/live/lKOPEf07BPk WEEK 04 Course-07 (16-OCT-24, at 08 P.M. GMT+2) Git, Jira, Bitbucket and CI/CD Pipelines https://youtube.com/live/qmQ0VAoOHKU Course-08 (20-OCT-24, at 10 A.M. GMT+2) Q&A https://youtube.com/live/egGuelCX-xQ WEEK 05 Course-09 (27-OCT-24, at 08 P.M. GMT+2) Good Coding Practices and Design Recommendations - 1/2 https://youtube.com/live/uS0JLgQ3YlU Course-10 (01-DEC-24, at 10 A.M. GMT+2) Q&A https://youtube.com/live/NBCqeq2elgM WEEK 06 Course-11 (18-DEC-24, at 08 P.M. GMT+2) Good Coding Practices and Design Recommendations - 2/2 https://youtube.com/live/OE6Eyv0LAJI Course-12 (22-DEC-24, at 10 A.M. GMT+2) Q&A https://youtube.com/live/q43MlpKOyUM