Latest Emerging Memory Developments At 2021 IEDM And MRAM Forum Including скачать в хорошем качестве

Latest Emerging Memory Developments At 2021 IEDM And MRAM Forum Including

This article covers some more interesting content from the 2021 IEEE IEDM and the MRAM Forum that followed the IEDM.  We look at some papers from the conference covering magnetic random-access memory (MRAM), ferroelectric RAM (FeRAM,) Phase Change Memory (PCM) as well as an equipment announcement by Hprobe for MRAM wafer testing.  We also talk a bit about presentations on in-memory computing approaches. CEA-Leti reported on a demonstration of 16-kbit ferroelectric random-access memory (FeRAM) arrays using a HfO2-based ferroelectric at the 130nm node.  The breakthrough includes back-end-of-line (BEOL) integration of TiN/HfO2:Si/TiN ferroelectric capacitors as small as 0.16 µm², and solder reflow compatibility for the first time for this type of memory.  In the CEA-Leti work, the team observed zero bit failure at the array level, with the memory window fully open down to 2.5 V programming voltage, and ultrafast switching speed down to four nanoseconds. Array-level endurance was also promising at up to 10 million cycles, as was array-level data retention at 125 °C for 104s (three hours).  The work was supported by the EU’s 3eFERRO Consortium project that was designed to produce new ferroelectric material Hf(Zr)O2 that makes FeRAM a competitive NVM candidate for IoT applications.  One of the co-authors is from NaMLab in Germany.  The image below shows the devices built by CEA-Leti. Several sessions at the IEDM and MRAM Forum explored developments in MRAM technology.  Researchers from Tohoku university fabricated a spin tunnel torque (STT)-MRAM magnetic tunnel junction (MTJ) as small as 2nm.   They also demonstrated device switching times as low as 3ns in sub-five nm STT MRAM MTJs.  Samsung spoke about trade-offs they made to create a 28nm CIS (CMOS image sensor)-Compatible embedded STT-MRAM for a frame buffer memory.  The device has a macro density of 13.94 Mb/square-mm.  The device had write speeds less than 50nm and endurance greater than 1010 cycles.  Retention time for buffer applications is about 1 second.  The image below compares three types of eMRAM memory to SRAM, eDRAM and eFlash in terms of latency and endurance. Renasas spoke about a 20Mb embedded STT-MRAM array in a 16nm FinFET logic process, achieving a 72% write energy reduction.   This was done by terminating write pulses adaptively according to the characteristics of each STT-MRAM cell.  IBM Research reported on an 80 Mb MRAM with 40nm junctions for last level cache using MRAM data scrubbing.  The data scrubbing improved endurance without impacting the chip error rate (CER) for last level cache applications.  They report that during MRAM data scrubbing, an error correction code (ECC) read/write is applied periodically to fix data retention errors, preventing bit error rate (BER) from accumulating beyond specs. By adjusting the data scrubbing scheme with tradeoffs in energy consumption, area, and data inaccessibility during data scrubbing, low chip error rate can be realized. All data is taken from the source: http://forbes.com Article Link: https://www.forbes.com/sites/tomcough... #mram #newstrump #newstodaydonaldtrump #newsworldabc #newstodayfox #bbcnewsworld #