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Fused Floating-Point Arithmetic for DSP Application

Fused Floating-Point Arithmetic for DSP Application Earl Swartzlander, Professor University of Texas, Austin, TX Earl Swartzlander spoke on Friday, October 29th, 2010 at 1:00PM in Biomanufacturing Training and Education Center (BTEC), Room 135 This talk describes the application of two fused floating-point operations to the implementation of important DSP applications. Floating-point arithmetic is a great advantage for DSP as it removes the need to address overflow, scaling and underflow problems that arise with fixed?point arithmetic. It simplifies interfacing the DSP to conventional microprocessors. Specific attention is focused on fast Fourier transform "butterfly" operations. The FFT "butterfly" operations consist of complex multiplications, additions and subtractions. Two new fused floating-point operations are a fused two-term dot product and a fused add?subtract unit. Both radix-2 and radix-4 butterflies can be implemented efficiently with the new fused operations. When placed and routed using high performance 45nm standard cells, the fused FFT radix-4 butterfly is about 13% faster and 26% smaller than a conventional implementation constructed with discrete floating-point adders and multipliers. The numerical results of the fused implementation are more accurate since the fused implementation uses fewer rounding operations. Earl E. Swartzlander, Jr. is a Professor of Electrical and Computer Engineering at the University of Texas at Austin. His research interests include: (1) the optimization of computer arithmetic and its application to general purpose and application specific processor design, (2) the interaction between VLSI technology and computer architecture, and (3) digital signal processor design and implementation. Previously he was with TRW Systems where he held a variety of positions including Director of Independent Research and Development for the TRW Defense Systems Group. He is a member of the Technical Advisory Board of the Electronics, Computing and Information Technology Centre (ECIT) at Queens University of Belfast. He is the editor of 7 books, the author or co?author of 65 journal papers, 270 conference papers, 33 book chapters and one book. He is a co-inventor of 4 patents and has 7 patents pending. He is currently the hardware area editor for ACM Computing Reviews and a member of the Editorial Board for the Journal of Signal Processing Systems. Previously, he was an Associate Editor of the IEEE Transactions on Parallel and Distributed Systems, the IEEE Journal of Solid-State Circuits, and the IEEE Transactions on Computers. He was the Editor-in-Chief of the Journal of VLSI Signal Processing, the IEEE Transactions on Computers, and the IEEE Transactions on Signal Processing. He is currently chair of the IEEE James H. Mulligan, Jr. Education Medal Committee. He was a member of the Board of Governors of the IEEE Signal Processing Society, the IEEE Solid-State Circuits Council/Society, and the IEEE Computer Society. He is a Fellow of the IEEE. He held a Howard Hughes Doctoral Fellowship. He has received a Golden Core award from the IEEE Computer Society and a Third Millennium Medal from the IEEE. He is a distinguished Engineering Alumnus of Purdue University and The University of Colorado.