Tessent DFT - Fault Coverage Accounting for Complex SoCs: Part 3 of 3 скачать в хорошем качестве

Tessent DFT - Fault Coverage Accounting for Complex SoCs: Part 3 of 3

Complex SoC designs typically consist of many physical design cores integrated together. When using Hierarchical Design-For-Test (DFT) techniques, all the Design for test steps are completed at the core level first before moving to the top level of the DFT design. This means there is test coverage information generated across many separate steps for each core which all has to be efficiently merged together into a single, comprehensive, and meaningful test coverage report. Part 3 of this Tessent DFT video series demonstrates how test coverage at the core level of a design is automatically forwarded to the SoC level when using pattern retargeting. The process for generating External mode patterns and test coverage results as well as merging Internal mode results from the core is described. Detailed descriptions of fault categories in the statistics report are provided and results are also viewed in the Design for test, DFT, Visualizer graphical interface. ______________________________________________________________________ ABOUT TESSENT SILICON LIFEYCYCLE SOLUTIONS Tessent Silicon Lifecycle Solutions (formerly Mentor Graphics/UltraSoc) is a division of Siemens EDA (Siemens Digital Industries Software). Tessent are widely recognized as the industry market leader in delivering design augmentation and linked applications that detect, mitigate and eliminate risks throughout the IC lifecycle. Tessent solutions help customers address their debug, test, yield, safety, security and optimization requirements for today’s most complex SoCs. Tessent solutions fall into 2 key categories, Tessent Test and Tessent Embedded Analytics. TESSENT TEST | Design for Test (DFT) and Yield Learning DFT and yield learning products for logic, memory and mixed-signal devices. The Tessent Test product suite provides comprehensive silicon test and yield learning applications that addresses the challenges of manufacturing test, debug, and yield ramp. TESSENT EMBEDDED ANALYTICS | SoC Debug and Analytics Tessent Embedded Analytics provides solutions for real-time debug and post-deployment analytics for RISC-V-based and other complex SoCs. _____________________________________________________________________ LEARN MORE Visit the Tessent website: www. https://eda.sw.siemens.com/en-US/ic/t... Email: tessent@siemens.com #DFTmarketleader