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How to use Loop and Exit in VHDL

Learn how to to create a loop in VHDL, and how to break out of it. There are several types of loops in VHDL. There is the implicit “process loop”, the While loop, and the For loop. And then there is the simple loop which is just called “Loop”. Blog post for this video: https://vhdlwhiz.com/loop-and-exit/ The syntax for the Loop statement in VHDL is: loop [code to loop through] end loop; The syntax for breaking out of a loop in VHDL is: exit; The Loop statement will cause the program to loop forever between the “loop” and “end loop;” statements. All kind of loops (except for the implicit process loop) can be broken out of by using the Exit statement. Loop statements are typically used in testbenches when you want a process to execute some code initially, and then loop forever over some other code. Example process with initial code: process is begin [code to be executed initially] wait for 50 ns; loop wait until rising_edge(Clk); [code to be executed forever at every clock cycle] end loop; end process; Loop and Exit statements can combined in testbenches where you want the program to loop over some code, and exit it based on some criteria. The Loop statement is equivalent to the "While true Loop" statement. Example of process which loops and restarts when some criteria is met: process is begin [code to be executed every time the process restarts] wait for 50 ns; loop wait until rising_edge(Clk); if [criteria for restarting the process] then exit; end if; [code to be executed every clock cycle] end loop; end process;