Making resettable registers and upgrading our Computer : CU+CPU PART 2 | DLS EP 31 скачать в хорошем качестве

Making resettable registers and upgrading our Computer : CU+CPU PART 2 | DLS EP 31

Logic for ROM, CU, and CPU to make a simple computer: making a resettable register in the process PART 2 CONTROL UNIT PROCESS SHEET: DATA OUT TASK Form: BBBB BBBB BBB Data: 4-bit input Output: 4-BIT DATA INPUT 0000 OUT JMP CTN 0001 OUT A reg 0010 OUT B reg 0011 RAM-16x4 synchronous out (needs 4-bit address from data) 0100 OUT SHIFT REG 0101 Next: outputting alu result of ADD 0110 SUB 0111 AND 1000 NOT 1001 NAND 1010 OR 1011 NOR 1100 XOR 1101 XNOR 1110 TASK/STORE: Store REG A 000 Store REG B 001 RAM Store (4-bit ADDRESS from data) 010 Store MAN JMP CTN 011 JMP CTN UP 100 JMP CTN DWN 101 Shift UP Store 110 Shift DWN Store 111 FIBONACCI PROGRAM: 0001 0000 000 (Store “1” in REG A) 0000 0110 011 (Store ADD result in JMP) 0000 0010 001 (Store A in REG B) 0000 0110 000 (Store ADD result in REG A) 0000 0110 011 (Store ADD result in JMP) 0000 0010 001 (Store A in REG B) 0000 0001 000 (Store JMP in REG A) 0000 0110 011 0000 0010 001 0000 0001 000 0000 0110 011 0000 0010 001 0000 0001 000 0000 0110 011 0000 0010 001 0000 0001 000 0000 0110 011 0000 0010 001 0000 0001 000 simulation: https://kshlok.itch.io/digital-logic-sim-v... https://sebastian.itch.io/digital-logic-sim Thanks ‪@ajax123z‬ and ‪@SebastianLague‬ ! Check out their content! Thanks for watching! It's been quite a journey to get this far: making a CPU out of AND and NOT gates. Good job if you've been following along! I reccommend checking out Sebastian Lague's original series : Exploring how computers work. #digitallogic .