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FPGA Implementation of Classification Algorithms for Deafness Detection in Newborn Babies This project showcases the implementation of classification algorithms for detecting deafness in newborns using FPGA technology. The system was developed on a ZedBoard Zynq-7000 from Xilinx. The primary objective was to detect deafness based on the cry signals of newborn babies. To achieve this, a classification system was trained using MATLAB. The final hyperparameters were then implemented on the FPGA. The design of the entire system is presented, illustrating the VHDL-designed blocks of the classification system. The process involves the synthesis of the project, which implements the system on the FPGA. The Implemented Design section demonstrates specific cells in the bitstream. In the feature extraction section, a one-second-length baby cry signal is displayed alongside a feature extracted via MATLAB simulation and FPGA implementation, yielding values of 1.709 and 1.707, respectively. For the classification process, all features from the entire signal are extracted. AdaBoost and Gaussian Mixture Model classifiers are employed to identify the type of signal. In this project, a final result of 1 indicates a normal baby cry signal, while a value of 0 represents an anomalous signal, allowing for the detection of deafness.