Analog layout of an op-amp using the Magic VLSI tool скачать в хорошем качестве

Analog layout of an op-amp using the Magic VLSI tool

Design repo: https://github.com/RTimothyEdwards/tu... 00:00:00 intro 00:00:34 getting started with the tutorial 00:01:48 load xschem 00:03:32 open magic 00:08:18 import all transistors 00:11:35 subcells / instances related to xschem 00:13:48 extra parameters 00:14:40 starting layout 00:16:05 pins 00:17:05 default ports 00:18:07 look at the netlist 00:19:50 manual port direction 00:20:22 layout discussion 00:21:32 jogging component position 00:22:16 rough positioning 00:31:24 keys for moving and copying 00:32:06 start with wiring 00:34:36 highlight difference in object style 00:35:09 save 00:35:55 bulk up LI with metal 00:36:24 contact them 00:38:02 checking what's connected to what 00:39:21 guard rings are automatic contacts 00:39:51 place the vcc pin 00:40:29 how Tim wires things 00:41:39 how thick to make traces 00:42:24 wiring 00:44:32 contacts for plus and minus 00:45:14 change pin to met2 00:45:48 Aligning fills 00:46:23 connecting bias transistor 00:48:07 which way to connect the transistors 00:49:05 continue layout 00:49:35 the wiring tool 00:50:23 fix the DRC spacing error 00:52:06 running wires over transistors 00:53:10 connecting with via1 00:54:56 minimum contact size DRCs 00:55:54 Altering an instance of a transistor 00:59:51 wiring xm54 01:06:01 mosfet source and drain are symetric 01:10:01 connecting the output 01:12:35 Wiring the adjust pin 01:13:28 Finding DRC errors 01:14:05 Air wires / fly wires would be helpful 01:15:14 Layout done 01:15:27 LVS 01:16:20 Running netgen 01:17:13 Debugging LVS 01:17:52 Removing zero value devices 01:19:03 Work around parasitics in the schematic 01:19:41 Correct number of devices but nets don't match 01:20:40 Finding the net error 01:21:16 Labelling in Magic to help debug LVS 01:26:06 Re-removing capacitors from schematic 01:26:30 One more error 01:29:07 Last LVS error 01:30:44 Do DRC errors prevent extraction? 01:31:36 LVS circuits match 01:32:00 LVS issues related to netgen development 01:33:05 How to compare extracted simulation against the schematic?