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JTAG boundary testing

JTAG boundary testing With the development of electronic industry and production value testing of electronic products becomes increasingly complicated. Familiar functional testing is becoming less informative because of the increasing complexity of printed circuit assemblies. For many years global electronics manufacturers have used a strategy of structural testing. It does not involve checking the functioning of product, but rather testing the quality of its assembly and compliance of design documentation. Tests themselves and their development are most often performed in automatic mode. One of the most popular methods for structural testing - in-circuit testing - is carried out using an automatic tester and a needle type contact field. If the tested card has sufficient contact areas, we can achieve almost one hundred percent test coverage - localization of dry joints, short circuits, checking the presence or absence of components, as well as measuring par values. But progress does not stand still. Electronics products are becoming smaller, and sometimes it is impossible to place even a couple of dozens of pads on a board with high-density mounting. In addition, there have appeared new types of housings, such as QFP, BGA, CSP, etc. Their outputs enable no test access with contact fields. In addition, a modern board can contain dozens of layers. Therefore a completely different approach in terms of access has lately become increasingly popular. It is called boundary scan. The method is based on testing boards through a special connector with JTAG (4-wire interface according to IEEE 1149.1 standard issued in 1990). The boundary-scan technology provides isolation of faults of a controlled electronic module and contacts it only in four test points (TDI, TCK, TMS, TDO). Another advantage of the boundary-scan is a significant performance improvement of the testing process by eliminating redundant searches for short circuits/breaks if the scanned chain passes the test successfully. If a device has one or more chips that support IEEE 1149.1 standard, you can test not only the circuit associated with these chips, but also other elements, including memory, logic, resistors and external connectors. When boundary-scan mode is applied, JTAG-components disable their logic and go to the test mode, allowing external hardware to manage its findings and test the circuit. Tools designed to test according to JTAG-interface allow you also to produce intersystem ...