Soitec SmartCut for SiC engineering substrate: SmartSiC(TM) - Walter Schwarzenbach (Soitec) скачать в хорошем качестве

Soitec SmartCut for SiC engineering substrate: SmartSiC(TM) - Walter Schwarzenbach (Soitec)

This lecture on wide band gap power transistors for electrified mobility was given by Walter Schwarzenbach of Soitec on the YESvGaN-TRANSFORM-PowerElec Phd summer school in Ghent, Belgium. More information about the summer school can be found here: https://yesvgan.eu/en/summer_school_2023 This summer school has been made possible through the support of the Flemish Government and the Doctoral Schools of Ghent University. The YESvGaN project has received funding by the ECSEL JU under Grant Agreement No 101007229. The TRANSFORM project has received funding by KDT JU under Grant Agreement No 101007237. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Germany, France, Belgium, Austria, Sweden, Spain, Italy. The PowerElec project has received funding by the EMPIR initiative (grant no 20IND09). The EMPIR initiative is co-funded by the European Union’s Horizon 2020 research and innovation programme and the EMPIR Participating States.