Preempt-RT Latency Benchmarking of the Cortex-A53 Processor - Paul Thomas, AMSC скачать в хорошем качестве

Preempt-RT Latency Benchmarking of the Cortex-A53 Processor - Paul Thomas, AMSC

Preempt-RT Latency Benchmarking of the Cortex-A53 Processor - Paul Thomas, AMSC ARMv8 processors are becoming more common in the industrial market. It is useful to understand how well these processors perform with Preempt-RT. AMSC looked at the CortexA53 utilized in the ZYNQ UlataScale+ processors form Xilinx. The Cortex-A53 is an ARMv8 processor with an 8-stage in-order pipeline. The performance was compared with a Cortex-A9, a 10+ stage out-of-order pipeline. Even with the difference in pipeline design in these two processors, it is an interesting comparison because it represents the evolution of Xilinx’s ZYNQ product line. Three different latency tests were performed: standard cyclictest latency, external hardware interrupt latency (as utilized by the IIO subsystem) and Ethernet UDP latency. Analyzing the performance of a hardware interrupt can be tricky, the method of utilizing a timer with a capture function is detailed in the presentation. About Paul Thomas Paul Thomas is the Lead Embedded Software Engineer at AMSC. Paul has over 15 years of experience working with embedded Linux. He has designed complex systems built on embedded Linux such as: the tracking system for large solar dishes and cellular based IoT connectivity solutions. At AMSC he leverages real-time embedded Linux to create distributed real-time control systems.