Operation of a two input NAND gate with totem pole output скачать в хорошем качестве

Operation of a two input NAND gate with totem pole output

For a standard TTL NAND gate, resistor connected at the collector of the output transistor causes increased propagation delay. This problem can be rectified using an active pull up resistor. In a totem pole pair, a transistor is used as the active pull up resistor which reduce the propagation delay. Whenever one or more inputs are at Logic 0, output is at Logic 1 and when both inputs of the NAND gate are at Logic 1, then output is at Logic 0. #ttl_nand_gate_with_totem_pole_output #TTL_NAND_gate_with_TOTEM_POLE_output #TTL_NAND_gate #Circuits_Analytica #circuits_analytica #CIRCUITS_ANALYTICA