TISHITU Design of Decoder IC using Transistors in Proteus Simulator скачать в хорошем качестве

TISHITU Design of Decoder IC using Transistors in Proteus Simulator

1. A decoder circuit composed of at least one current switch means which provides current to either one of two output terminals in response to an input signal applied to an input terminal of said at least one current switch means, a charging circuit means including output emitter follower transistors for pulling up the signal level of said output terminals, and at least one multi-emitter transistor with its base and collector being commonly connected to form a junction, emitters of which are connected to the corresponding output terminals of said current switch means and said charging circuit means, wherein the improvement comprises: the output emitter follower and multi-emitter transistors being structurally designed so that the voltage across the base and the emitter regions of said at least one multi-emitter transistor is larger than the voltage across the base and the emitter regions of each of said emitter follower transistors. 2. A decoder circuit according to claim 1, wherein the emitter area of said emitter follower transistor is larger than the emitter area of said multi-emitter transistor. 3. A decoder circuit according to claim 1, wherein the total amount of the impurities of the intrinsic base region of said multi-emitter transistor is larger than the total amount of the impurities of said emitter follower transistor. 4. A decoder circuit according to claim 1, wherein one of said output terminals will have a positive voltage level when current is applied to it and the other of said output terminals will have a negative voltage level when current is applied to it. 5. A decoder circuit composed of at least one current switch means which provides current to either one of two output terminals in response to an input signal applied to an input terminal of said at least one current switch means, a charging circuit means including output emitter follower transistors for pulling up the signal level of said output terminals, and at least one diode group in which the anodes of a plurality of diodes are commonly connected and the cathode terminals of said diodes are connected to the corresponding output terminals of said current switch means and said charging circuit means, wherein the improvement comprises: the forward threshold voltages of said diodes being larger than the voltage across the base and emitter regions of said emitter follower transistor. 6. A decoder circuit according to claim 5, wherein said diodes are composed of polycrystalline silicon. 7. A decoder circuit according to claim 5, wherein said diodes are a plurality of connected Schottky barrier diodes wherein each of said diode forward threshold voltages comprises the forward voltages of at least two serially-connected Schottky barrier diodes. 8. A decoder circuit according to claim 5, wherein one of said output terminals will have a positive voltage level when current is applied to it and the other of said output terminals will have a negative voltage level when current is applied to it. BACKGROUND OF THE INVENTION This invention relates to an integrated circuit, and more particularly to a decoder circuit for a semiconductor memory. High-speed decoder circuits using transistors or diodes are already known, and are actually used in LSI circuits for memory. For example, a decoder circuit in which transistors are connected as diodes is described on pages 78-79 of the article "Ultra High Speed 1K-Bit RAM with 7.5 ns Access Time" by H. Mukai and K. Kawarada (IEEE International Solid-State Circuits Conference 1977). Such a decoder circuit in the prior art is shown in FIG. 1. This decoder circuit essentially consists of a decoder transistor QD and a current switch which is composed of transistors Qs1 and Qs2. In this current switch, current Is flows through either the transistor Qs1 or Qs2 depending on the voltage level of an input VIN1. When all the current switch transistors which are connected to the emitters of a transistor QD such as the transistor Qs1 are off, the output Vout becomes high. There is only one combination in which an off-transistor of the current switch is connected to all the emitters of the transistor QD, in the other transistors QD at least one emitter being connected to an on-transistor. Therefore, current flows through a resistor RD to which QD is connected and the outputs of the decoders become low-level. ~-~~-~~~-~~-~ Please watch: "Lifi Communication by Arduino UNO Download Project"    • Lifi Communication by Arduino UNO Download...   ~-~~-~~~-~~-~