Should I Learn Verilog or VHDL? скачать в хорошем качестве

Should I Learn Verilog or VHDL?

Should I learn Verilog or VHDL? They are both perfectly good HDLs for programming and modeling FPGA. They are both industry standard hardware description languages. At least there is only one TLA in that sentence. TLA? What is that? Three letter acronym. Which language should I learn? Verilog has been used a lot longer than VHDL. VHDL came out in 1987, while Verilog goes back to 1983. That's not a big difference when you consider it was 30 years ago. Whereas JavaScript frameworks showed up in 2009 and 2010, and a 12 month head start is a big deal. Verilog is probably easier to learn, assuming you don't need to learn PLI. What is PLI? The Programming Language Interface. Verilog sometimes only does as good a job at modeling as VHDL when using PLI too. Which one is easier to learn? VHDL is not like C, which for a lot of people is a plus. Then again, it gives you a steep learning curve because it is not as intuitive. Which one is easier to use? I've heard Verilog is easier because it has fewer roles. It feels like you can learn Verilog faster because you can get going, but you don't find the error later until you're in the simulation phase. VHDL lets you use a lot of data types. Verilog data types are a lot simpler, if limited. Using Verilog means you have to be careful how you compile it. Change the order of the files and you can get very different results. A lot of the hassle can be made up for by code re-use. Which one lets me recycle files and minimize re-inventing the wheel -- or circular circuit? VHDL has more design reusability. Verilog needs functions and procedures put in different file systems to be used again. Why is VHDL better? VHDL uses libraries to store entities, architectures and configurations. This makes it ideal when you have multiple design projects. I guess that's because Verilog was designed as an interpretive language. But it doesn't translate well to today's engineering environment.