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Presenter: Mikey Shahar, DFT Architect and Integration Senior Technical Lead at Intel | U2U Summit Presentation | Learn how Intel Corporation have reduced test time and brought down product costs by using the Tessent Streaming Scan Network, SSN, with high speed IO test port. With recent developments in interconnect technologies giving a boost to disaggregated products with 2.5D or 3D (and beyond construction), Mikey also explains some of the challenges of testing disaggregated parts and the testing strategy applied to disaggregated products in Intel client. _______________________________________________________________ ABOUT TESSENT SILICON LIFEYCYCLE SOLUTIONS Tessent Silicon Lifecycle Solutions is a division of Siemens EDA (Siemens Digital Industries Software). Tessent are widely recognized as the industry market leader in delivering design augmentation and linked applications that detect, mitigate and eliminate risks throughout the IC lifecycle. Tessent solutions help customers address their debug, test, yield, safety, security and optimization requirements for today’s most complex SoCs. Tessent solutions fall into 2 key categories, Tessent Test and Tessent Embedded Analytics. TESSENT TEST | Design for Test (DFT) and Yield Learning DFT and yield learning products for logic, memory and mixed-signal devices. The Tessent Test product suite provides comprehensive silicon test and yield learning applications that addresses the challenges of manufacturing test, debug, and yield ramp. TESSENT EMBEDDED ANALYTICS | SoC Debug and Analytics Tessent Embedded Analytics provides solutions for real-time debug and post-deployment analytics for RISC-V-based and other complex SoCs. _______________________________________________________________ LEARN MORE Visit the Tessent website: https://eda.sw.siemens.com/en-US/ic/t... Email: [email protected] #Tessent #DFTmarketleader