Optimizing power and timing of RISC-V - IP, Processors and systems скачать в хорошем качестве

Optimizing power and timing of RISC-V - IP, Processors and systems

This recording is of a Hands-on Workshop on the architecture exploration of RISC-V based products. The end-product can be a IP or core, SoC or a system such as SSD Controller or a IoT device. This Hands-on-Workshop educates the attendees on the use of RISC-V in various application and to evaluate the feasibiloty of new products using RISC-V. RISC-Vis an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. RISC-V has features to increase computer speed, yet reduce cost and power use. These include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, simplified standards-based floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. Sign extension is said to often be on the critical timing path. The instruction set is designed for a wide range of uses. It is variable-width and extensible so that more encoding bits can always be added. It supports three word-widths, 32, 64, and 128 bits, and a variety of subsets. The definitions of each subset vary slightly for the three word-widths. The subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.