An Efficient Implementation of TensorFlow Lite for RISC-V Vectors - Mostafa Hagog, SiFive скачать в хорошем качестве

An Efficient Implementation of TensorFlow Lite for RISC-V Vectors - Mostafa Hagog, SiFive

An Efficient Implementation of TensorFlow Lite for RISC-V Vectors - Mostafa Hagog, SiFive When deploying a neural network (NN) as part of a low-power edge application such as mobile or IoT devices, designers must trade-off flexibility and power efficiency. Hard-wired accelerators are often chosen for their inherent parallelism and performance; however, accelerators are rigid, may be difficult to program, and are not necessarily suited for some NNs that can’t take advantage of the parallelism provided. Conversely, general-purpose processors, ubiquitous in edge applications, may lack the compute efficiency needed under a strict power budget. A third option is a processor, optimized for parallelizable workloads, that can scale to many-core to deliver the necessary performance of multiple tera-ops per second that machine learning algorithms may require. Consequently, demand for vector-enabled, general-purpose processors that are compiler-friendly is rapidly growing. Using the widely deployed MobileNet CNN as an example, SiFive will demonstrate a TensorFlow Lite solution optimized for RISC-V vectors and then further boosted by more than 10X in some cases with SiFive Intelligence Extensions. For more info about RISC-V, a free and open ISA enabling a new era of processor innovation through open standard collaboration, see: https://riscv.org/