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Investigating how the data bus behaves when you read from unmapped I/O locations. It was interesting, and I don't fully understand the end result! Here's the stardot forum thread about this: https://stardot.org.uk/forums/viewtop... And a link to the circuit diagram for the BBC Micro: http://mdfs.net/Info/Comp/BBC/Circuit... The address decode logic is in the top centre of the diagram, and IC23 in particular is gathering up all the chip select signals for "slow" I/O devices in order to decide whether or not to stretch the clock, so that's a good place to look if you want to know whether something is fast or slow. The 6522 VIA that I removed from the machine is IC69 (looks like 59 in the diagram!) in the centre left, connected to the printer and user ports, and IC73 in the centre right is the ADC. The floppy disc controller that was already missing is IC70 in the top left. In the video I referred to a transceiver between the CPU data bus and the RAM data bus - the RAM chips are in a 4x4 grid at the bottom centre of the diagram, and the transceiver is IC14, just up and right from there. You can also see the pull-down resistors next to that.