[FPGA 2021] An FPGA-based 7-ENOB 600 MSample& скачать в хорошем качестве

[FPGA 2021] An FPGA-based 7-ENOB 600 MSample&

Lukas Leuenberger, OST Eastern Switzerland University of Applied Sciences Dorian Amiet, OST Eastern Switzerland University of Applied Sciences Tao Wei, University of Rhode Island Paul Zbinden, OST Eastern Switzerland University of Applied Sciences Analog to digital converters (ADCs) are indispensable nowadays. Analog signals are digitized earlier and earlier in the processing chain to reduce the need for complex analog signal processing. For this reason, ADCs are often integrated directly into field-programmable gate arrays (FPGA) or microprocessors. However, such ADCs are designed for a specific set of requirements with limited flexibility. In this paper, a new structure of an FPGA-based ADC is proposed. The ADC is based on the slope ADC, where a time-to-digital converter (TDC) measures the time from the beginning of a reference slope until the slope reaches the voltage-to-be-measured. Only FPGA-internal elements are used to build the ADC. It is fully reconfigurable and does not require any external components. This innovation offers the flexibility to convert almost any digital input/output (I/O) into an ADC. Considering the very high number of digital I/O ports available in today's FPGA systems, this enables the construction of a massive and powerful ADC array directly on a standard FPGA. The proposed ADC has a resolution of 9.3 bit and achieves an effective number of bits (ENOB) of 7 at a sample rate of 600 MSample/s. The differential nonlinearity (DNL) ranges from -0.9 to 0.9 bit, and the integral nonlinearity (INL) is in the range between -1.1 and 0.9 bit. An alternative version of the ADC operates at 1.2 GSample/s and achieves an ENOB of 5.3. ACM Digital Library: https://dl.acm.org/doi/10.1145/343192... Created with Clowdr: https://clowdr.org/