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This video walks through the Common Source amplifier with a resistive load, a foundational nMOS stage used in analog ICs and discrete designs. We start from the topology and operating intuition, then build the small-signal model to derive voltage gain without channel length modulation and see why the stage behaves like an inverting transconductor feeding a resistor. Next, we bring channel length modulation into the picture to show how the finite output resistance lowers gain and why bias point and headroom matter for linear operation in saturation. We then analyze input and output resistances under practical biasing schemes. You will see how battery bias compares to a voltage-divider network, how the protecting (coupling) capacitor preserves DC bias while passing AC signals, and how each choice shapes input impedance and midband gain. We finish with a worked exercise where you compute the gain and check that the device remains in saturation using the small-signal parameters extracted at the chosen bias point. 0:00 Topology 0:49 Gain no Channel Length Modulation 6:29 Gain with Channel Length Modulation 8:35 Input Resistance with battery bias 11:09 Input Resistance with voltage divider bias 12:24 Input Resistance with voltage divider bias and protecting capacitor 13:25 Output Resistance with no Channel Length Modulation 14:28 Output Resistance with Channel Length Modulation 15:43 Exercise; gain and saturation