Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE скачать в хорошем качестве

Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE

By Adeel Ahmad, 10xEngineers. Nouman Amir, 10xEngineers. Ahmad Tameem Kamal, 10xEngineers. Bilal Zafar, 10xEngineers. Saad Bin Nasir, 10xEngineers. Abstract: This project aims to enable RISC-V microkernel support in the IREE Machine Learning Compiler. It includes enabling the lowering of the MLIR operations to IREE microkernel calls and implementing microkernel functions for RISC-V. A comprehensive analysis of RISC-V ISA would also be provided as part of the project to identify areas where it lags behind x86 and ARM when targeting GenAI models. This project is a work in progress, and hence, the proposed methodology is discussed in the extended abstract. We aim to improve the RISC-V software ecosystem and spark community interest in expanding RISC-V support in ML compilers and kernel libraries.