Presentation by TESTONICA - FPGA Based System For Pre Silicon IJTAG DFT Validation скачать в хорошем качестве

Presentation by TESTONICA - FPGA Based System For Pre Silicon IJTAG DFT Validation

Recorded at the Siemens U2U Europe Summit 2023. Presenter: ARTUR JUTMAN, Director, Testonica Abstract: The recent accelerated adoption of IEEE Std. 1687 (aka IJTAG) by key players of the semiconductor industry is being driven by maturing EDA tool support, whereas Siemens EDA Tessent is amongst the pioneering solutions that paved the way to early adopters, while providing today a full-featured DFT and embedded instrumentation ecosystem based on IJTAG standard. In this contribution, we describe a workflow based on Tessent that enabled implementing an FPGA-based reference system for pre-silicon evaluation and validation of a target IJTAG infrastructure as well as validation of the tool ecosystem to be used in production or during in-field maintenance. The resulting system is an HDL design implemented inside the reconfigurable logic of an FPGA. The design contains several dozens of instruments integrated into an IJTAG network, which in its turn is accessible via standard FPGA’s JTAG test access port. Even though the platform is implemented on FPGA, it provides an ability to work with IJTAG in the same manner as it would be on an ASIC with IEEE 1687 support. The implemented IJTAG network has multiple layers of hierarchy and arranges the instruments into four sub-networks of various interconnection topology. The network provides read/write or just read access to internal registers (some general-purpose and some built-in resources such as on-chip temperature and voltage sensors) as well as outwards-oriented instruments connected to external LEDs and switches on the board. The design is written in VHDL language, synthesized using Xilinx Vivado toolchain, simulated in ModelSim environment and validated with TESSENT. The atomic modules of IJTAG network are described in the standard IEEE 1687 ICL (Instrument Connectivity Language) format as well as the network interconnect structure generated from HDL. A set of PDL (Procedural Description Language) procedures has also been prepared, whereas each PDL is accompanied with respective re-targeted IEEE Std. 1149.1 (JTAG) patterns. These patterns target FPGA’s 1149.1 TAP port which is described in the topmost ICL module of the IJTAG network. This enables usage of standard JTAG tools from a preferred vendor as well as evaluation of such tools in context of IJTAG operations. This case study is a result of collaboration between Testonica and ADVANTEST. The talk will review the work done and the lessons learned. Bio: Artur Jutman is the founder and Managing Director of Testonica Lab since 2005. He has a PhD degree in computer engineering TU Tallinn, Estonia. His professional focus embraces such topics as diagnostic and defect modeling, test optimization, embedded test instrumentation, test firmware, BIST, DFT as well as both ASIC and system test in a broad sense - all yielding over 160 peer-reviewed research papers published. Dr. Jutman has co-ordinated several EU-funded research projects on test-related topics, participated in organizing test conferences and workshops across Europe as well as given several keynotes, invited talks, embedded and full tutorials at international conferences and symposia. He is a member of the steering committees of European Test Symposium and the Nordic Test Forum society. ______________________________________________________________________ ABOUT TESSENT SILICON LIFEYCYCLE SOLUTIONS Tessent Silicon Lifecycle Solutions (formerly Mentor Graphics/UltraSoc) is a division of Siemens EDA (Siemens Digital Industries Software). Tessent are widely recognized as the industry market leader in delivering design augmentation and linked applications that detect, mitigate and eliminate risks throughout the IC lifecycle. Tessent solutions help customers address their debug, test, yield, safety, security and optimization requirements for today’s most complex SoCs. Tessent solutions fall into 2 key categories, Tessent Test and Tessent Embedded Analytics. TESSENT TEST | Design for Test (DFT) and Yield Learning DFT and yield learning products for logic, memory and mixed-signal devices. The Tessent Test product suite provides comprehensive silicon test and yield learning applications that addresses the challenges of manufacturing test, debug, and yield ramp. TESSENT EMBEDDED ANALYTICS | SoC Debug and Analytics Tessent Embedded Analytics provides solutions for real-time debug and post-deployment analytics for RISC-V-based and other complex SoCs. _____________________________________________________________________ LEARN MORE Visit the Tessent website: www. https://eda.sw.siemens.com/en-US/ic/t... Email: tessent@siemens.com #Tessent #DFTmarketleader