DTALK - Cryogenic Operation of Planar & Multigate Fully Depleted SOI MOSFETs-Prof. Marcelo Pavanello скачать в хорошем качестве

DTALK - Cryogenic Operation of Planar & Multigate Fully Depleted SOI MOSFETs-Prof. Marcelo Pavanello

The aggressive scaling of MOSFET dimensions triggered the search for alternative solutions for the traditional planar transistors for future technological nodes. Also, the advent of Quantum Computing raised the interest in the cryogenic operation of ultimate MOSFETs to be applied in interface circuits between the Qbits and the remaining electronic systems. Planar and tridimensional MOSFETs operating with fully depleted (FD) silicon fabricated in Silicon-On-Insulator (SOI) substrates are among the technological solutions being widely investigated. Triple-gate Ω-shaped MOSFETs with fin height and width of similar dimensions, in the order of 10-15nm, commonly referred to as nanowires (NWs) in the literature, are promising contenders. More recently, stacked NWs also appeared as a viable technological alternative to increase the current density per footprint. Due to their tridimensional architecture, NWs and stacked NWs have been shown to promote improved control of the channel charges, leading to reduced short channel effects and great scalability, which results in excellent electrical properties for both digital and analog applications. Moreover, due to their nanometer-size channel, quantum transport can be evidenced in aggressively scaled nanowires at cryogenic temperatures. On the other hand, planar thin-film FD SOI MOSFETs achieved the maturity for mass production and are also considerable alternatives for Quantum Computing. In this scenario, this talk will present and discuss the operation of some technological contenders for Quantum Computing when exposed to cryogenic temperatures down to 4 K. Peculiarities of these devices while operating in the cryogenic regime, such as transconductance oscillations indicating carrier confinement and self-heating will be presented.