Presentation by Intel - Tessent SSN Silicon Bring up скачать в хорошем качестве

Presentation by Intel - Tessent SSN Silicon Bring up

Recorded at Siemens U2U Europe Summit 2023. Presenter: OFRI BRENROTH, DFT Lead, Intel Abstract: Intel NEX-NCNG (Network and Edge Compute Cloud Connectivity Group) Devices has very aggressive Schedule and Test costs goals. Tessent Streaming Scan Network (SSN) advantages on Test-Time cost reduction was important to be used but we had to address the impact on our DFT and Physical design flows. To reach SSN implementation, we had to work back-to-back with the Full-Chip Architectures and Physical designers alongside the Test Engineers and their requirements and limitations, involving all aspects of pre-Si Simulations to post-Si debug and validation. To increase our confidence level on our first SSN product we enabled a Debug feature that leans on the SSN clock routing. By doing so we were able to observe some of our SSN scan signals at the ATE level. Bio: Ofri Brenroth has worked at INTEL since 2011. He started as a Test-Engineer for 6 Years and since then he has worked as a DFT engineer and Project DFT lead. One of INTEL's key moto's is "Customer Orientation", and since the ATETest-Engineering team are the DFT main customer, having that experience as a former Test-Engineer, helps elevate his understanding of the Customer's needs and limitations. Ofri has a Bachelor Degree in Electrical Engineering majoring in VLSI. ______________________________________________________________________ ABOUT TESSENT SILICON LIFEYCYCLE SOLUTIONS Tessent Silicon Lifecycle Solutions (formerly Mentor Graphics/UltraSoc) is a division of Siemens EDA (Siemens Digital Industries Software). Tessent are widely recognized as the industry market leader in delivering design augmentation and linked applications that detect, mitigate and eliminate risks throughout the IC lifecycle. Tessent solutions help customers address their debug, test, yield, safety, security and optimization requirements for today’s most complex SoCs. Tessent solutions fall into 2 key categories, Tessent Test and Tessent Embedded Analytics. TESSENT TEST | Design for Test (DFT) and Yield Learning DFT and yield learning products for logic, memory and mixed-signal devices. The Tessent Test product suite provides comprehensive silicon test and yield learning applications that addresses the challenges of manufacturing test, debug, and yield ramp. TESSENT EMBEDDED ANALYTICS | SoC Debug and Analytics Tessent Embedded Analytics provides solutions for real-time debug and post-deployment analytics for RISC-V-based and other complex SoCs. _____________________________________________________________________ LEARN MORE Visit the Tessent website: www. https://eda.sw.siemens.com/en-US/ic/t... Email: [email protected] #Tessent #DFTmarketleader