Logic Synthesis of RTL | Synopsys Design Compiler | Synopsys DC | dc_shell | DC Tutorial скачать в хорошем качестве

Logic Synthesis of RTL | Synopsys Design Compiler | Synopsys DC | dc_shell | DC Tutorial

This is the session-5 of RTL-to-GDSII flow series of video tutorial. In this session, we have demonstrated the synthesis flow of Synopsys Design compiler in the command line. We have started from the RTL code which has been checked for functionality and using the technology library and design constraints we have synthesized the RTL code into gate level netlist. During this logic synthesis process, our RTL code has been translated, optimized and mapped to the standard cells of the technology library. In this video, we have performed all the steps using command only, but a similar video using GUI mode only of Design compiler has been demonstrated in S-6 of this series. In this RTL-to-GDSII flow of video series, there are total 10 sessions. We have covered all the stages of ASIC design using EDA tools demonstration and also the basic theories. Part-wise descriptions of the different session and the link of videos are as follow. 1. Session-1: Overview of RTL to GDSII flow | Basic terms in the flow Video link:    • RTL to GDSII flow | Basic terminology used...   2. Session-2: Flow in EDA tool's perspective | Different EDA tools | various files Video link:    • ASIC Flow and EDA tools | Various files us...   3. Session-3: Functional verification of RTL | using Synopsys VCS | VCS demo Video link:    • RTL Design & Simulation | Synopsys VCS Tut...   4. Session-4: Logic Synthesis flow | RTL to gate-level netlist | Design compiler Video link:    • Logic Synthesis flow | RTL Synthesis flow ...   5. Session-5: Logic Synthesis | Design Compiler | Command-line | gate level netlist Video link:    • Logic Synthesis of RTL | Synopsys Design C...   6. Session-6: Logic Synthesis | Design Compiler | GUI Mode| design_vision Video link:    • Logic Synthesis in Design Compiler | GUI M...   7. Session-7: Logic Equivalence Check using Formality |S8| RTL-to-GDSII flow | Formality tutorial Video link:    • Logic Equivalence Check | Synopsys Formali...   8. Session-8: Physical Design Flow | PnR flow |RTL-to-GDSII flow | innovus flow Video link:    • Physical Design Flow | PnR flow | RTL-to-G...   9. Session-9: Design Import | Physical Design |RTL-to-GDSII flow | innovus tools tutorial Video link:   • Design Import | Cadence Innovus | GUI of I...   10.Session-10: Place and Route in Cadence Innovus | full PnR flow | Cadence Innovus demo Video link:    • Place and Route in Cadence  Innovus | full...   ====Connect with us========================== All on one page: https://www.teamvlsi.com/p/contact_8.... Blog: https://www.teamvlsi.com Facebook Page:   / teamvlsi   WhatsApp Group: https://chat.whatsapp.com/C6etLHR6oAf... Telegram Group: https://t.me/teamvlsi (Or search team VLSI on telegram) Email: teamvlsi2014@gmail.com ============================== #LogicSynthesis #SynopsysDesignCompiler #TeamVLSI